1. Field of Invention
The present invention relates to semiconductor memories and in particular simultaneous read and write operation.
2. Description of Related Art
Some buffer memory applications such as for use with a LCD controller require simultaneous read and write operations. In these applications different memory blocks are chosen for the read and write operations. One approach is to have a decoder associated with each memory block which requires considerable chip area. Another approach uses a dual port memory cell which requires dual wordlines and dual bit lines and again requires a large chip area.
U.S. Pat. No. 6,052,327 (Reddy et al.) is directed to a dual port programmable logic device memory array data is written into the device using a write column decoder and data selection logic, and data is read from the device using a read column decoder and data selection logic. U.S. Pat. No. 5,999,478 (Proebsting) is directed to tri-port memory buffers with fast fall through capability and methods of operation. The tri-port memory has a read port, a write port and a bi-directional input and output port. U.S. Pat. No. 5,982,700 (Proebsting) is directed to buffer memory arrays having nonlinear columns to provide parallel data access capability. U.S. Pat. No. 5,978,307 (Proebsting) is directed to integrated circuit memory devices with multi-port memory arrays for increasing data bandwidth. U.S. Pat. No. 5,781,480 (Nogle et al.) is related to a pipelined dual port integrated circuit memory. A control circuit controls access to the memory cells where simultaneous requests for access are serviced sequentially within a single cycle. U.S. Pat. No. 5,016,214 (Laymoun) is directed to memory cells with separate read and write paths using two pairs of bit lines.
In FIG. 1 is shown a memory with multiple array sections 10, 11, and 15 of prior art that allows a read from a first memory array section and a write to a second memory array section. Each memory array section has a separate wordline decoder 13, 14 and 12. A read and write multiplexer 16 under the control of a read and write controller 17 permits the reading of data from on array section while a second array section is being written. The multiple wordline decoders 13, 14 and 12 require a large chip area to implement and an alternative design is needed to reduce the size of the chip area needed to implement the simultaneous read and write capability.
It is an objective of the present invention to provide a memory using conventional memory cells with simultaneous read and write capability. It is also an objective of the present invention to provide the simultaneous read and write capability with a reduction in the required chip area. It is further an objective of the present invention to provide a separate read and write path. It is also an objective of the present invention to provide a memory with a plurality of sections and to enable one section for a write operation while enabling a second section for a read operation. It is still further an objective of the present invention to have separate read and write wordlines and to multiplex the read and write wordlines at each section of the memory.
In the present invention a multi-section memory using conventional memory cells is disclosed in which each section of the memory has a wordline multiplexer. Connected to each multiplexer are outputs from a read wordline decoder and a write wordline decoder. The wordline multiplexer for each section chooses a read wordline or a write wordline to be connected to the section. Separate write and read data paths are connected to each memory section to accommodate read and write operations.